Variations such as process, voltage, temperature, IR drop, and so forth, may have an impact on an integrated circuit. In general, these variations may alter the performance of circuitry in the integrated circuit. Therefore, an integrated circuit may fail to operate properly over an entirety of possible variations, even though it is functionally correct and manufactured within tolerances.
In general, on-chip variation (OCV) is a timing-analysis methodology that may be used to analyze integrated circuit timing due to fabrication process variations on circuitry in the integrated circuit. OCV may allow circuit designers to ensure that their circuit designs will continue to meet design criteria in light of expected process variations of the fabrication process used to create the integrated circuit.
Typically, fabrication process variations may occur at different levels. Some fabrication process variations may remain relatively consistent for an entire fabrication process, while others may vary between different wafer lots but are consistent for a single lot of wafers. Other fabrication process variations may occur between wafers of a single wafer lot, and yet others may vary on a single wafer. Finally, some may occur within a single integrated circuit chip.
Examples of fabrication process variations that may occur within a single integrated circuit may include mask variations, etching variations, optical proximity variations, and so forth. Generally, many of these variations may occur over a small area, potentially impacting one portion of a circuit while not affecting another portion of the same circuit. These variations may result in problems such as, signal setup, signal hold, clock gating, and so forth.
A prior art technique commonly referred to as statistical static timing analysis (SSTA) makes use of Monte Carlo simulation techniques with a circuit simulation application, such as Spice, making use of fabrication process models to computing timing performance for an integrated circuit. Monte Carlo simulation technique may compute a range of performance numbers for the integrated circuit from process variation information provided in the fabrication process model. SSTA may consume a considerable amount of time to perform, however, since a wide range of possible process variations must be simulated.
A prior art technique commonly referred to as static timing analysis STA with OCV (STA+OCV) uses a constant timing de-rating factor that may be applied to each timing path element in a timing path of an integrated circuit, for example, each buffer in a buffer chain, to compute a minimum and a maximum timing for the timing path. The constant timing de-rating factor may be a manufacturing process dependent value. Then, a variety of possible combinations of positive and negative contributions of the timing de-rating factor on each timing path element in the timing path may be analyzed to determine the minimum and the maximum timing for the integrated circuit. If the integrated circuit meets design criteria, then the integrated circuit may be considered as having passed STA+OCV analysis. STA+OCV does not consider the number of timing path elements when it is assigning a timing de-rating factor, potentially leading to timing analysis results that are inaccurate, especially for small or large numbers of timing path elements.